Power-on-reset (POR) circuits are numerous and commonly function to provide a signal in response to the presence of a predetermined voltage level. Since POR circuits commonly operate to control devices coupled to a multiplexed or shared data bus of a processor controlled data system, the output of the POR circuit must be enabled until the system is properly initialized. POR circuits allow other circuits in the system such as bus drivers to remain disabled until the system is under sufficient control of the processor to function properly. Known POR circuits are typically either level triggered or step response triggered but usually do not have both capabilities. Level triggered POR circuits have the disadvantage of providing pulse widths which may be too narrow to reset circuitry when very fast transitioning signals occur. A POR output pulse having a minimum pulse width is typically very desirable. Step response triggered POR circuits however have the disadvantage of not being very sensitive and do not always provide a retriggering output in response to a single voltage level transition. Other known POR circuits are also susceptible to erroneously responding to transient noise spikes coupled to the circuit via the supply voltage.